HOMEWORK
- Combinational Logic (due Sep 29)
- Sequential Logic (assigned Sep 29, due Oct 6)
- Processor Architecture (assigned Nov 17, due Nov 24)
LABS
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- Verilog Basics (Aug 22)
- Download and install tools (Xilinx ISE Webpack) BEFORE FRIDAY’S LAB SESSION
- Full installer for Windows
- Full installer for Linux
- Installers are ~6 GB, so allow several hours (overnight) to download
- Mac users must use Bootcamp (harder to make the tools work with Parallels)
- See Piazza for installation tips if you are having problems
- Assignment
- Hierarchical Design & Verilog Practice (Aug 29)
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- Assignment and test fixture (Lab2_test.v)
- Verilog Primer
- Refer to the Verilog references (links to the right)
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- Designing a complete ALU (Sep 5)
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- Assignment and test fixture (Lab3_test.v)
- Refer to these slides (from Comp411) for ALU details
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- Sequential Design: Counters (Sep 12)
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- Assignment and test fixtures (CounterMod4_test.v, CounterMod7_test.v, CounterMod7Reset_test.v and xycounter_test.v)
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- Working with the boards! (Sep 19)
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- Assignment and Verilog files (dec7seg.v and segdisplay.ucf)
- Read the board manual: Nexys 3 / Nexys 4
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- Finite-State Machines: A Stop Watch (Sep 26)
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- Assignment
- Verilog files: Part 0 (display4digit.v), Part 2 (seebounce.v), Part 3 (debouncer.v), Part 4 (fsm_3blocktemplate.v)
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- VGA Displays (Oct 3)
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- Assignment
- Part 1 files: vgatimer.v and vgatimer_test.v
- Part 2 files: vgadisplaydriver.v and vgadisplaydriver_test.v
- More Part 1 and 2 files: vgadisplaydriver.ucf, display10x4.v, display640x480.v and display800x600.v. NOTE: A sync polarity of “1” means a negative sync pulse (i.e., normally “1”, but goes down to “0” during the sync).
- Very good reference for VGA display timing
- UPDATE (10/6): The displayXXxYY.v files have been refreshed. Also, a self-checking Verilog test fixture for the “toy” 10×4 display is available now: vga10x4_selfchecking.v
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- Working with Memories (Oct 10)
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- Assignment
- Verilog files: ram.v and Lab8.ucf
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- A Basic Datapath (Oct 24)
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- Assignment
- UPDATE (10/29): A self-checking Verilog test fixture is available now for those who are still having trouble with this assignment: Lab9_test.v
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- A Full Single-Cycle CPU (Oct 31)
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- Assignment
- MIPS instruction set reference (“green card”)
- Test 1 (Summing integers): assembly (test1.asm), hex code (test1.txt)
- Test 2 (Summing an array): assembly (test2.asm), hex code (test2.txt), and data (test2_data.txt). UPDATE (11/13): A more detailed self-checking Verilog test fixture for Test 2 is available now for those who are still having trouble with this assignment: test2_selfchecking.v
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- Final Project – Part A (Nov 5)
- Assignment
- Comp411 Slides
- Demo proposal: Please submit on Sakai by Wed Nov 12, 5pm. Look to the left under “Assignments”
- Project demo ideas (demos from Spring 2012)
- UPDATE (11/16): A self-checking test fixture for jal/jr is now available. The program recursively computes the square of a number: assembly (sqr.asm), hex code (sqr_imem.txt), data (sqr_dmem.txt), and Verilog (mips_test_sqr.v).
- Final Project – Part B (Nov 14)
- Assignment
- (NEW) Bitmap memory hex generation script (by Zach Cross): Readme and Python script
- I/O devices
- keyboard (plugs into USB port): Verilog files (keyboard.v, keyboard_test.v, display4digit.v, keyboard.ucf)
- joystick (add-on): Reference manual, Verilog files
- accelerometer (add-on for Nexys 3): Reference manual, Verilog files
- accelerometer (built-in for Nexys 4): See Nexys 4 manual, ask my help for Verilog.
- keypad (add-on): Reference manual, Verilog files
- stereo audio amplifier (add-on): Manufacturer info, Reference manual, ask my help for Verilog.
- Clock divider: Use the following files to generate a slower clock:
- clockdiv.v: Verilog source for clock division (for Nexys 3 and Nexys 4)
- top.v: skeleton for top-level module using the slower clock
- Introduction (Aug 20)
- Reading: Ch. 1.1-1.4
- Combinational Logic – 1 (Aug 25)
- Reading: Ch. 1.5-1.6
- Combinational Logic – 2 (Aug 27)
- Reading: Ch. 2.1-2.3
- Combinational Logic – 3 (Sep 3)
- Reading: Ch. 2.2-2.6
- Transistors (Sep 8)
- Reading: Ch. 1.7-1.8
- Combinational Logic – 4 (Sep 10-15)
- Reading: Ch. 2.7-2.9
- Sequential Logic – 1: Basics (Sep 17)
- Reading: Ch. 3.1-3.3 and Ch. 5.4.1
- State Machines – 1 (Sep 22)
- Reading: Ch. 3.3-3.4
- State Machines – 2: Verilog (Sep 24-29)
- Reading: Ch. 3.4 and Ch. 4.6
- VGA Displays (Oct 1)
- Reading: Board manual pages on VGA display
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- QUIZ #1 (Wed Oct 1 in class)
- Material covered: Lectures 1-9 (plus readings), Labs 1-5
- 15 minutes in duration
- Open-book, open-notes, calculator allowed
- Flip-Flop Timing (Oct 6)
- Reading: Ch. 3.5.1-3.5.3
- Memories – 1 (Oct 8, 15)
- Reading: Ch. 5.5
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- QUIZ #2 (Wed Oct 8 in class)
- Material covered: Lectures 7-11 (plus readings), Labs 5-7
- 15 minutes in duration
- Open-book, open-notes, calculator allowed
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- MIDTERM EXAM (Mon Oct 13 in class)
- Material covered: Lectures 1-12 (plus readings), Homework #1-#2, Labs 1-7
- 75 minutes in duration
- There will be a take-home component as well (extra credit)
- Open-book, open-notes, calculator allowed
- No computer/internet access, except for accessing class website, lecture slides and Verilog references
- Memories – 2 (Oct 20)
- Reading: Ch. 5.5
- Arithmetic Circuits (Oct 22)
- Reading: Ch. 5.2.1-5.2.2
- Datapath and Single-Cycle MIPS (Oct 27)
- Reading: Ch. 7.1-7.3
- Reading: Ch. 6 (review of MIPS ISA)
- Adding Memory and I/O Devices (Oct 29)
- Reading: Ch. 8.1 and 8.5
- More on I/O Devices (Nov 3)
- Multicycle MIPS (Nov 10)
- Reading: Ch. 7.4
- Pipelined MIPS (Nov 12-17)
- Reading: Ch. 7.5
- QUIZ #3 (Fri Nov 14 in lab session)
- Material covered: Lectures 12-15 (plus readings), Labs 8-10
- 15 minutes in duration
- Open-book, open-notes, calculator allowed
- Interrupts, DMA and I/O (Nov 19)
- Reading: Ch. 7.7
- QUIZ #4 (Fri Nov 21 in lab session)
- Material covered: Lectures 16-20 (plus readings), Labs 8-10
- 15 minutes in duration
- Open-book, open-notes, calculator allowed
- Wrap Up (Nov 24)
- Project Demos (Dec 1)
- First batch of ~20 demos
- 3-4 minutes per student
- Open to the department
- Project Demos (Dec 3)
- Second batch of ~20 demos
- 3-4 minutes per student
- Open to the department
- FINAL EXAM (Mon Dec 8, 12-3pm)
- Material covered: All lectures (plus readings), labs, project and homework. Greater emphasis on post-midterm exam material.
- Open-book, open-notes, calculator allowed
- No computer/internet access, except for accessing class website, lecture slides and Verilog references
- MIDTERM EXAM (Mon Oct 13 in class)
- QUIZ #2 (Wed Oct 8 in class)
- QUIZ #1 (Wed Oct 1 in class)
LECTURES
- Verilog Basics (Aug 22)
