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HOMEWORK

  1. Combinational Logic (due Sep 29)
  2. Sequential Logic (assigned Sep 29, due Oct 6)
  3. Processor Architecture (assigned Nov 17, due Nov 24)

 

LABS

  1. Verilog Basics (Aug 22)
  2. Hierarchical Design & Verilog Practice (Aug 29)
  3. Designing a complete ALU (Sep 5)
  4. Sequential Design: Counters (Sep 12)
  5. Working with the boards! (Sep 19)
  6. Finite-State Machines: A Stop Watch (Sep 26)
  7. VGA Displays (Oct 3)
  8. Working with Memories (Oct 10)
  9. A Basic Datapath (Oct 24)
    • Assignment
    • UPDATE (10/29): A self-checking Verilog test fixture is available now for those who are still having trouble with this assignment:   Lab9_test.v
  10. A Full Single-Cycle CPU (Oct 31)
  11. Final Project – Part A (Nov 5)
  12. Final Project – Part B (Nov 14)

 

LECTURES

  1. Introduction (Aug 20)
    • Reading:  Ch. 1.1-1.4
  2. Combinational Logic – 1 (Aug 25)
    • Reading:  Ch. 1.5-1.6
  3. Combinational Logic – 2 (Aug 27)
    • Reading:  Ch. 2.1-2.3
  4. Combinational Logic – 3 (Sep 3)
    • Reading:  Ch. 2.2-2.6
  5. Transistors (Sep 8)
    • Reading:  Ch. 1.7-1.8
  6. Combinational Logic – 4 (Sep 10-15)
    • Reading:  Ch. 2.7-2.9
  7. Sequential Logic – 1: Basics (Sep 17)
    • Reading:  Ch. 3.1-3.3 and Ch. 5.4.1
  8. State Machines – 1 (Sep 22)
    • Reading:  Ch. 3.3-3.4
  9. State Machines – 2: Verilog (Sep 24-29)
    • Reading: Ch. 3.4 and Ch. 4.6
  10. VGA Displays (Oct 1)
    • Reading: Board manual pages on VGA display
  • QUIZ #1 (Wed Oct 1 in class)
    • Material covered: Lectures 1-9 (plus readings), Labs 1-5
    • 15 minutes in duration
    • Open-book, open-notes, calculator allowed
  1. Flip-Flop Timing (Oct 6)
    • Reading: Ch. 3.5.1-3.5.3
  2. Memories – 1 (Oct 8, 15)
    • Reading: Ch. 5.5
  • QUIZ #2 (Wed Oct 8 in class)
    • Material covered: Lectures 7-11 (plus readings), Labs 5-7
    • 15 minutes in duration
    • Open-book, open-notes, calculator allowed
  • MIDTERM EXAM (Mon Oct 13 in class)
    • Material covered: Lectures 1-12 (plus readings), Homework #1-#2, Labs 1-7
    • 75 minutes in duration
    • There will be a take-home component as well (extra credit)
    • Open-book, open-notes, calculator allowed
    • No computer/internet access, except for accessing class website, lecture slides and Verilog references
  1. Memories – 2 (Oct 20)
    • Reading: Ch. 5.5
  2. Arithmetic Circuits (Oct 22)
    • Reading:  Ch. 5.2.1-5.2.2
  3. Datapath and Single-Cycle MIPS (Oct 27)
    • Reading:  Ch. 7.1-7.3
    • Reading: Ch. 6 (review of MIPS ISA)
  4. Adding Memory and I/O Devices (Oct 29)
    • Reading:  Ch. 8.1 and 8.5
  5. More on I/O Devices (Nov 3)
  6. Multicycle MIPS (Nov 10)
    • Reading:  Ch. 7.4
  7. Pipelined MIPS (Nov 12-17)
    • Reading:  Ch. 7.5
  • QUIZ #3 (Fri Nov 14 in lab session)
    • Material covered: Lectures 12-15 (plus readings), Labs 8-10
    • 15 minutes in duration
    • Open-book, open-notes, calculator allowed
  1. Interrupts, DMA and I/O (Nov 19)
    • Reading:  Ch. 7.7
  • QUIZ #4 (Fri Nov 21 in lab session)
    • Material covered: Lectures 16-20 (plus readings), Labs 8-10
    • 15 minutes in duration
    • Open-book, open-notes, calculator allowed
  1. Wrap Up (Nov 24)
  2. Project Demos (Dec 1)
    • First batch of ~20 demos
    • 3-4 minutes per student
    • Open to the department
  3. Project Demos (Dec 3)
    • Second batch of ~20 demos
    • 3-4 minutes per student
    • Open to the department
  • FINAL EXAM (Mon Dec 8, 12-3pm)
    • Material covered: All lectures (plus readings), labs, project and homework. Greater emphasis on post-midterm exam material.
    • Open-book, open-notes, calculator allowed
    • No computer/internet access, except for accessing class website, lecture slides and Verilog references

Fall 2014 Course Website